Personal computers ("PCs") generally comprise a microprocessor central processing unit ("CPU") and memory and input/output ("I/O") subsystems. The CPU is the PC's processing center of activity, assigned the responsibility of performing basic calculations on data stored in the computer's memory. The memory subsystem provides volatile primary storage space for programs or data to be processed by the CPU. The I/O subsystem provides nonvolatile secondary storage, such as disk storage.
The speed of interaction between the CPU and memory and I/O subsystems significantly governs the speed at which the PC can process and store information. In particular, the shorter the time required for memory access, the faster the CPU can retrieve data to be executed and the faster the CPU can return the processed data to memory.
To achieve faster effective memory access, the prior art has provided the concept of cache memory. A cache memory is a relatively fast memory that resides logically between the CPU and a cached memory. The purpose of cache memory is to increase the effective access speed of the main memory by avoiding the need for some accesses to the main memory. Cache memories operate by providing fast-access storage for a small portion of the data stored in the main memory. If the CPU wishes to read data that happens to be contained in the cache memory, a cache "hit" occurs, avoiding the need to access the main memory. If the cache memory does not happen to contain the data, a cache "miss" occurs, requiring a lengthier access to the main memory. Obviously, selection of the data to store in the cache memory requires intelligent guessing and is the subject of much inventive attention.
Caches are typically small relative to the main memory, because the relatively fast memory that constitutes cache memory is concomitantly relatively expensive. If all memory could be constructed out of the same fast memory used for caches, there would not be a need for a cache. Cache memory is therefore an efficient, cost-effective way of using a small amount of very fast memory to optimize effective memory access speed.
Therefore, on higher performance systems, the memory subsystem is often layered and includes both a main memory and a main memory cache, each of which are coupled through a host bus of the PC. Likewise, on such higher performance systems, the I/O subsystem may also be layered and thus include not only the disk storage, but a disk cache interposed between the disk storage and the CPU. Since the memory subsystem primary memory is directly coupled to the CPU through the host bus, in general, the primary memory realizes a dramatically shorter access time than the secondary memory.
With respect to write accesses, cache memories may operate in either a write-through mode or in a write-back mode. In a write-through mode, memory writes are made concurrently to both the cache memory and the main memory. Write-through caching is regarded as a conservative method of caching, because writes are concurrent and there is no risk that the main memory contains obsolete data. Unfortunately, because writes to the main memory continue as though no cache memory were in place, decreases in effective access time are only realized in reads from the main memory.
In a write-back mode, writes are made only to the cache memory. Periodically, the cache memory is "flushed" to the main memory and obsolete data in the main memory is thus superseded in a batch. Since data is written to the main memory in a "burst" when the cache memory is flushed, bus utilization is more efficient. Therefore a write-back cache is faster than a write-through cache.
However, write-back cacheing is risky; if power to the cache memory is lost while the cache memory contains data as yet unwritten to the main memory, that unwritten data is lost. When power is restored, the main memory contains obsolete data.
On very high performance systems, such as local area network ("LAN") servers, it is most advantageous to operate in a write-back mode. However, the associated risk of data loss is intolerable. Because cost is less a factor in such very high performance systems, the prior art provides battery backup systems to protect the write-back cache memory as against power loss. The battery backup system continues to power the cache memory for a predetermined period of time after a power outage. As a result, the user is assured, for a limited time, that the current data in the write-back cache memory is safe.
Since it is vital that the user know how long the battery backup system will function to protect the user's data, prior art battery backup systems incorporate a visual indicator to instruct the user of the battery charge or life status. For example, some battery backup systems employ an expensive liquid crystal display ("LCD") to inform the user of the status of the battery backup system. Other PCs use a bar or "ladder" light-emitting diode ("LED") display, comprising a plurality of individually-activatable LEDs, to inform the user of the status of the battery backup system. In both of these prior art battery backup systems, the battery status indicators and their associated drive circuitry are relatively complex and expensive.
Accordingly, what is needed in the art is a battery charge or life indicator for cache memory subsystems that is relatively simple and inexpensive in construction without sacrificing the indicator's ability adequately to inform the user of remaining battery charge or life.